Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

stc.d CP#, Rp[disp], CRs

*(Rp + (ZE(disp8) << 2)) = CP#(CRd+1:CRd);
# ∈ {0, 1, …, 7}

Rev1+

111010111010

Rp

CP #

1

CRs[3:1]

0

disp8

12

4

3

1

3

1

8

2

stc.d CP#, Rp++, CRs

*(Rp) = CP#(CRd+1:CRd);
Rp = Rp+8;
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

0

CRs[3:1]

001110000

12

4

3

1

3

9

3

stc.d CP#, Rb[Ri<<sa], CRs

*(Rb + (Ri << sa2)) = CP#(CRd+1:CRd);
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

1

CRs[3:1]

011

sa2

Ri

12

4

3

1

3

3

2

4

4

stc.w CP#, Rp[disp], CRs

*(Rp + (ZE(disp8) << 2)) = CP#(CRd);
# ∈ {0, 1, …, 7}

Rev1+

111010111010

Rp

CP #

0

CRs

disp8

12

4

3

1

4

8

5

stc.w CP#, Rp++, CRs

*(Rp) = CP#(CRd);
Rp = Rp+4;
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

0

CRs

01100000

12

4

3

1

4

8

6

stc.w CP#, Rb[Ri<<sa], CRs

*(Rb + (Ri << sa2)) = CP#(CRd);
# ∈ {0, 1, …, 7}

Rev1+

111011111010

Rp

CP #

1

CRs

10

sa2

Ri

12

4

3

1

4

2

2

4

Description

Stores the source register value to the location specified by the addressing mode.

Status Flags:

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Example:

stc.d
CP2, R2[0], CR0